Simulation of networked multicore systems

Provided by: Mohammed Abuteir (University Siegen)

The simulation of networked multi-core chips is a significant research problem in large embedded applications.  Although multi-core processors in embedded systems offer increased computational resources and performance, many applications still require distributed systems with multiple of these processors to satisfy resource requirements and provide fault-tolerance at system level.

DREAMS introduces a framework for the co-simulation of a distributed system (i.e., off-chip networks, end systems) with multi-core chips based on networks-on-a-chip. Simulation components are introduced for the synchronization and data exchange between these simulators. A realization was performed using the simulator GEM5 for the chip level, the simulator OPNET for the cluster level, the simulation OVPSim for the hypervisor  and components for communication and synchronization via TCP/IP.  Evaluations based on different use cases demonstrate the utility of the framework to analyse applications and their timing on networked multi-core chips.

Simulation environments play an important role for system architects who explore design decisions of platforms, applications and potential interference. Several simulation environments exist in the state-of-the-art for multi-core processors (e.g., based on GEM5 [1] or SystemC). Likewise, the simulation of networked embedded systems is addressed in the state-of-the art (e.g., [2], [3], [4]).

However, the simulation of networked multi-core chips including both the chip-level and the off-chip level is an open research problem. Such a simulation framework supporting multiple integration levels is required to gain an understanding of embedded systems on those platforms.

A major contribution of DREAMS is a framework supporting the simulation builing blocks and co-simulation techniques for the chip, cluster and hypervisor levels. We consider multi-core chips based on a message-based Network-on-Chip (NoC), where messages need to be exchanged between NoCs and off-chip networks. We propose building blocks for the synchronization and data exchange between the respective discrete event simulators. Local simulation controllers determine when dependencies in the co-simulation are satisfied in order to perform a simulation step.


Figure 1 shows an instantiation of the simulation framework for an example system encompassing a cluster of multi-core chips interconnected by a TTEthernet network.

Figure 1 Simulation Model of Virtual Platform

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[2] M. O. A. Cervin, D. Henriksson, TrueTime 2.0 beta 5 – Reference Manual, Department of Automatic Control, Lund University, Sweden, June 2010.

[3] M. Abuteir and R. Obermaisser, “Simulation environment for Time-Triggered Ethernet,” in IEEE International Conference on Industrial Informatics (INDIN), 2013, pp. 642–648.

[4] S. Buschmann, T. Steinbach, F. Korf, and T. C. Schmidt, “Simulationbased Timing Analysis of FlexRay Communication at System Level,” in SIMUTools 2013 – 6th International OMNeT++ Workshop. New York, USA: ACM DL, March 5-8 2013, pp. 285–290.